Welcome to my personal page. Currently I am working on my PhD thesis at Institut Polytechnique de Paris under the supervision of Florian Brandner and Lirida Naviner.
My main research interest is on using formal methods to design hardware. My latest experience is on developping memory controllers and cryptographic modules using the Coq proof assistant.
Other areas of expertise are: RISC-V processor design & optimisation, critical and mixed-criticality Real-Time Embedded Systems, DRAM scheduling, static analysis, concurrent programming, trusted execution environements (TEEs), bare metal development & micro-controllers.
I've also developped a few small projects on other topics, such as: AI, distributed systems, cloud, robotics, connected objects, ultra-low-power electronic design, and mobile networks.
You can download my CV here. You can also visit my Google Scholar page or my Linkedin page.
Best Paper Award (RTNS, 2022).
1st place at the 1st National RISC-V student contest (Paris, France, 2021). Organised by Thales, CNFM, and the GdR SOC2.
CAPES BRAFITEC Excellence Double Degree Fellowship (Belo Horizonte, Brazil, 2018). Granted by CAPES.
1st place at CoRA, the Autonomous Robot Competition (Belo Horizonte, Brazil, 2016). Organised by PETEE, School of Enginering, UFMG. Along with two teamates, I’ve designed a high speed line follower robot. Our robot’s performance granted us first place in the competition. You can check out the video from the championship round here. The software running on it is here.
Superscalar Processor Timing Anomalies Detector. A software written in C to detect timing anomalies in super-scalar processor trace executions.
RISC-V National Competition. My changes on the Ariane processor that awarded my first place on the 1st National RISC-V student contest.
Proficiency: C, and the Coq Theorem Prover.
Working level: SystemVerilog, Python, C++, Java.
Basic knownledge: Matlab, HTML, CSS, SQL, Haskell, OCaml, F*, UPPALL, TLA+.